The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order to keep the trigger rate acceptable (i. e.: < 1MHz). In order to extract the track information within the latency constraints (< 5 mu s), a custom real-time system is necessary. We developed a prototype of the main building block of this system, the Pattern Recognition Mezzanine (PRM) that combines custom Associative Memory ASICs with modern FPGA devices. The architecture, functionality and test results of the PRM are described in the present work.

Track Finding Mezzanine for Level-1 Triggering in HL-LHC Experiments

MAGAZZU', GIULIA;L (Storchi;Gian Mario);
2017-01-01

Abstract

The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order to keep the trigger rate acceptable (i. e.: < 1MHz). In order to extract the track information within the latency constraints (< 5 mu s), a custom real-time system is necessary. We developed a prototype of the main building block of this system, the Pattern Recognition Mezzanine (PRM) that combines custom Associative Memory ASICs with modern FPGA devices. The architecture, functionality and test results of the PRM are described in the present work.
978-1-5090-4386-6
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11564/670636
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